The goals of integrated circuit design are not only to create a nominal circuit design that meets a set of predetermined specifications, but also to ensure that the circuit design can be manufactured reliably. Numerous sources of variation may cause some instances of a completed circuit design (e.g., fully simulated or fabricated microchips) to fail, that is, to not achieve at least one of the predetermined design specifications. (Quite often, “testing” actually refers to full simulation prior to actual fabrication; that nomenclature is adopted in this description for simplicity.) Designers therefore seek to model such variation to estimate and reduce the susceptibility of manufactured designs to such failure.
Many methodologies for modeling variation are known in the art, including but not limited to those described in the related patents previously incorporated by reference. Once an acceptably accurate variation model or “performance model” for a manufacturing process has been established, a number of Monte Carlo test samples may be selected according to the performance model and simulated to determine if particular design instances will fail. Even with recent advances in simulation technology however, performing a large number of Monte Carlo simulation runs of a design may still be computationally expensive.
When the performance model is sufficiently accurate, the problem of designing for manufacturability often shifts from estimating a yield to determining if the yield is above or below a yield target with a particular level of confidence. Monte Carlo simulation is therefore often used with a significance test, to check if a design's yield is above a particular yield target y with a confidence level c. Higher confidence levels denote an increased sureness that a particular outcome is not due to chance.
When a yield target is high, verifying the yield requires a large number of samples when the actual yield is above or only slightly below the target yield. For example, a three-sigma Gaussian process corresponds to only a 0.13% probability of a failure occurring. Thus, because failures are so rare for such processes, many samples that do not fail will occur before one that does. If the actual yield of a manufactured design is one, so no failures actually occur, verifying that the yield exceeds the three-sigma level, e.g., 99.87%, requires the following approximate number of samples for the confidence levels shown:
CONFIDENCE LEVELNUMBER OF SAMPLES80%120090%170095%2200
Reducing the number of Monte Carlo simulation samples required to confidently compare a yield to a target yield is therefore important for final overall design verification. In the related patent application incorporated by reference above, embodiments estimate the overall failure probability of a number of statistical samples based on a performance model, then simulate the samples in decreasing failure probability order. This approach helps ensure that those samples most likely to fail will be simulated first, thus reducing the number of Monte Carlo simulation samples required to determine if a design yield is above a given yield target with a given confidence.
Many design iterations may occur however before a completed design is ready for a final overall yield verification that involves checking that all of the design specifications have been met. Designers instead often focus on one particular design specification at a time when developing and adjusting various portions of a circuit design. This approach helps designers “divide and conquer” the overall design problem into intuitively manageable aspects. Designers may thus frequently need to quickly determine if a design will meet a particular design specification even in the worst case variation scenario for that design specification.
To that end, rather than run a full Monte Carlo verification of an entire set of design specifications during each design iteration, designers may instead test a design to see if it meets a particular design specification properly in the most demanding design corner. Designers therefore need to reliably extract the worst statistical sample for a given design specification at the minimum computational expense. Designers may for example be able to trade off different aspects of circuit performance to help meet a more difficult design requirement, but they need to know the limits of such an exchange.
Further, if a circuit design is able to meet each design specification separately under the worst conditions for that specification during a given design iteration, the design is more likely to later meet an overall yield target that considers all design specifications together. That is, if even the worst combinations of inputs cannot make the circuit operate improperly in a given way, it will be more likely that nothing can. Conversely, any failure to meet a particular design specification is likely to doom the circuit design to failure when a full verification that checks all the design specifications is attempted.
Accordingly, the inventors have developed a novel way to help circuit designers and design tool vendors find the worst Monte Carlo simulation sample for use as a design corner to substitute for a full design verification during design iterations.